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ispLSI 2032VE
3.3V In-System Programmable High Density SuperFASTTM PLD Features
* SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC -- 1000 PLD Gates -- 32 I/O Pins, Two Dedicated Inputs -- 32 Registers -- High Speed Global Interconnect -- Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. -- Small Logic Block Size for Random Logic -- 100% Functional, JEDEC and Pinout Compatible with ispLSI 2032V Devices * 3.3V LOW VOLTAGE 2032 ARCHITECTURE -- Interfaces With Standard 5V TTL Devices * HIGH PERFORMANCE E2CMOS(R) TECHNOLOGY -- fmax = 225 MHz Maximum Operating Frequency -- tpd = 4.0 ns Propagation Delay -- Electrically Erasable and Reprogrammable -- Non-Volatile -- 100% Tested at Time of Manufacture -- Unused Product Term Shutdown Saves Power * IN-SYSTEM PROGRAMMABLE -- 3.3V In-System Programmability Using Boundary Scan Test Access Port (TAP) -- Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic -- Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality -- Reprogram Soldered Devices for Faster Prototyping * 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE * THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs -- Enhanced Pin Locking Capability -- Three Dedicated Clock Input Pins -- Synchronous and Asynchronous Clocks -- Programmable Output Slew Rate Control -- Flexible Pin Placement -- Optimized Global Routing Pool Provides Global Interconnectivity * ispDesignEXPERTTM - LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING -- Superior Quality of Results -- Tightly Integrated with Leading CAE Vendor Tools -- Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZERTM -- PC and UNIX Platforms
(R)
Functional Block Diagram
A0
Output Routing Pool (ORP)
Input Bus
A2
GLB
Logic Array
DQ
DQ
A5
DQ
A3
A4
0139Bisp/2000
Description
The ispLSI 2032VE is a High Density Programmable Logic Device that can be used in both 3.3V and 5V systems. The device contains 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2032VE features in-system programmability through the Boundary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. The ispLSI 2032VE offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2032VE device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. A7 (see Figure 1). There are a total of eight GLBs in the ispLSI 2032VE device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device.
Copyright (c) 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
2032ve_07
1
Input Bus
A1
DQ
A6
Output Routing Pool (ORP)
Global Routing Pool (GRP)
A7
Specifications ispLSI 2032VE
Functional Block Diagram
Figure 1. ispLSI 2032VE Functional Block Diagram
GOE 0
Output Routing Pool (ORP)
Output Routing Pool (ORP)
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 TDI/IN 0 TDO/IN 1
A0
A7
I/O 31 I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25 I/O 24 I/O 23 I/O 22 I/O 21 I/O 20 I/O 19 I/O 18 I/O 17 I/O 16
A1
Input Bus
A2
A5
A3
A4
TMS/NC BSCAN
Note: *Y1 and RESET are multiplexed on the same pin
Y0 Y1* TCK/Y2
0139B/2032VE
The device also has 32 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, output or bidirectional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. Device pins can be safely driven to 5 Volt signal levels to support mixed-voltage systems. Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connected together to make a Megablock (see Figure 1). The outputs of the eight GLBs are connected to a set of 32 universal I/O cells by the ORP. Each ispLSI 2032VE device contains one Megablock. The GRP has as its inputs the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew.
Clocks in the ispLSI 2032VE device are selected using the dedicated clock pins. Three dedicated clock pins (Y0, Y1, Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the outputs of the ispLSI 2032VE are individually programmable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a programmable fuse. The default configuration when the device is in bulk erased state is totem-pole configuration. The open-drain/totem-pole option is selectable through the ispDesignEXPERT software tools.
2
CLK 0 CLK 1 CLK 2
Generic Logic Blocks (GLBs)
Input Bus
Global Routing Pool (GRP)
A6
Specifications ispLSI 2032VE
Absolute Maximum Ratings 1
Supply Voltage Vcc .................................. -0.5 to +5.4V Input Voltage Applied ............................... -0.5 to +5.6V Off-State Output Voltage Applied ............ -0.5 to +5.6V Storage Temperature .............................. -65 to +150C Case Temp. with Power Applied .............. -55 to 125C Max. Junction Temp. (TJ) with Power Applied ... 150C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL PARAMETER Supply Voltage Input Low Voltage Input High Voltage Commercial Industrial TA = 0C to + 70C TA = -40C to + 85C MIN. 3.0 3.0 VSS - 0.5 2.0 MAX. 3.6 3.6 0.8 5.25 UNITS V V V V
VCC VIL VIH
Table 2-0005/2032VE
Capacitance (TA=25C, f=1.0 MHz)
SYMBOL PARAMETER Dedicated Input Capacitance I/O Capacitance Clock Capacitance TYPICAL 8 6 10 UNITS pf pf pf TEST CONDITIONS VCC = 3.3V, VIN = 0.0V VCC = 3.3V, VI/O = 0.0V VCC = 3.3V, VY = 0.0V
Table 2-0006/2032VE
C1 C2 C3
Erase Reprogram Specifications
PARAMETER Erase/Reprogram Cycles MINIMUM 10,000 MAXIMUM - UNITS Cycles
Table 2-0008A/2032VE
3
Specifications ispLSI 2032VE
Switching Test Conditions
Input Pulse Levels Input Rise and Fall Time 10% to 90% Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GND to 3.0V 1.5 ns 1.5V 1.5V See Figure 2
Table 2-0003/2032VE
Figure 2. Test Load
+ 3.3V R1 Device Output R2 C L* Test Point
Output Load Conditions (see Figure 2)
TEST CONDITION A B Active High Active Low Active High to Z at VOH -0.5V Active Low to Z at VOL +0.5V R1 316 R2 348 348 348 348 348 CL 35pF 35pF 35pF 5pF 5pF
*CL includes Test Fixture and Probe Capacitance.
0213A/2032VE
316
316
C
Table 2-0004A/2032VE
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL PARAMETER Output Low Voltage Output High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current BSCAN Input Low Leakage Current I/O Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current CONDITION IOL= 8 mA IOH = -4 mA 0V VIN VIL (Max.) (VCC - 0.2)V V VCC IN VCC VIN 5.25V 0V VIN VIL 0V VIN VIL VCC = 3.3V, VOUT = 0.5V VIL = 0.0V, VIH = 3.0V -300/-225 fTOGGLE = 1 MHz Others MIN. - 2.4 - - - - - - - - TYP. - - - - - - - - 80 65
3
MAX. UNITS 0.4 - -10 10 10 -150 -150 -100 - - V V A A A A A mA mA mA
VOL VOH IIL IIH IIL-isp IIL-PU IOS1 ICC2, 4, 5
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using two 16-bit counters. 3. Typical values are at VCC = 3.3V and T = 25C. A 4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum ICC . 5. Unused inputs at VIL = 0V.
Table 2-0007/2032VE
4
Specifications ispLSI 2032VE
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST COND. A A A - - - A - - A - A - B C B C - -
3
# 1 2 3 4 5 6 7 8 9
DESCRIPTION
1
-225 4 - - 225
1
-180 - - 180 125 200 3.0 - 0.0 4.0 - 0.0 - 4.0 - - - - 2.5 2.5 5.0 7.5 - - - - 4.0 - - 5.0 - 6.0 - 10.0 10.0 5.0 5.0 - -
MIN. MAX. MIN. MAX. 4.0 6.0 - - - - 3.0 - - 4.0 - 5.0 - 7.0 7.0 3.5 3.5 - -
UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl
1. 2. 3. 4.
Data Propagation Delay, 4PT Bypass, ORP Bypass Data Propagation Delay Clock Frequency with Internal Feedback 2 Clock Frequency with External Feedback ( tsu2 + tco1) Clock Frequency, Max. Toggle GLB Reg. Setup Time before Clock, 4 PT Bypass GLB Reg. Clock to Output Delay, ORP Bypass GLB Reg. Hold Time after Clock, 4 PT Bypass GLB Reg. Setup Time before Clock
154 250 2.5 - 0.0 3.5 - 0.0 - 3.5 - - - - 2.0 2.0
10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay, ORP Bypass 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Global OE Output Enable 17 Global OE Output Disable 18 External Synchronous Clock Pulse Duration, High 19 External Synchronous Clock Pulse Duration, Low
Unless noted otherwise, all parameters use a GRP load of 4, 20 PTXOR path, ORP and Y0 clock. Standard 16-bit counter using GRP feedback. Reference Switching Test Conditions section. -225 speed grade supercedes earlier -200. All parameters other than fmax (internal) are the same.
Table 2-0030A/2032VE
5
Specifications ispLSI 2032VE
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST COND. A A A - - - A - - A - A - B C B C - -
3
# 1 2 3 4 5 6 7 8 9
DESCRIPTION
1
-135 - - 135
1
-110 - - 111 77.0 125 5.5 - 0.0 7.5 - 0.0 - 6.5 - - - - 4.0 4.0 10.0 13.0 - - - - 5.0 - - 6.5 - 12.5 - 14.5 14.5 7.0 7.0 - -
MIN. MAX. MIN. MAX. 7.5 10.0 - - - - 4.5 - - 5.5 - 9.0 - 12.0 12.0 6.0 6.0 - -
UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl
Data Propagation Delay, 4PT Bypass, ORP Bypass Data Propagation Delay Clock Frequency with Internal Feedback Clock Frequency, Max. Toggle GLB Reg. Setup Time before Clock, 4 PT Bypass GLB Reg. Clock to Output Delay, ORP Bypass GLB Reg. Hold Time after Clock, 4 PT Bypass GLB Reg. Setup Time before Clock
2
Clock Frequency with External Feedback ( tsu2 + tco1)
100 167 4.0 - 0.0 5.5 - 0.0 - 5.0 - - - - 3.0 3.0
10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay, ORP Bypass 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Global OE Output Enable 17 Global OE Output Disable 18 External Synchronous Clock Pulse Duration, High 19 External Synchronous Clock Pulse Duration, Low
1. Unless noted otherwise, all parameters use a GRP load of 4, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section.
Table 2-0030B/2032VL
6
Specifications ispLSI 2032VE
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER Inputs #
2
DESCRIPTION
-225
-180
MIN. MAX. MIN. MAX. - - - - - - - - - 0.8 1.7 - - - - 0.5 - - - - - - - - - - 0.6 1.3 0.7 1.2 1.2 2.2 2.2 2.2 0.0 - - 0.7 1.3 3.2 4.2 2.8 1.3 0.3 1.2 2.0 1.5 1.5 2.0 0.8 1.0 2.2 - - - - - - - - - 0.9 2.1 - - - - 1.4 - - - - - - - 1.5 1.7 - 0.8 1.5 0.7 1.8 2.1 3.1 3.1 3.1 0.2 - - 0.8 1.3 4.0 5.7 3.6 1.4 0.4 1.3 2.0 2.8 2.8 2.2 1.5 1.7 3.0
UNITS
tio tdin
GRP
20 Input Buffer Delay 21 Dedicated Input Delay 22 GRP Delay 23 4 Product Term Bypass Path Delay (Combinatorial) 24 4 Product Term Bypass Path Delay (Registered) 25 1 Product Term/XOR Path Delay 26 20 Product Term/XOR Path Delay 27 XOR Adjacent Path Delay
3
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tgrp
GLB
t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck
ORP
28 GLB Register Bypass Delay 29 GLB Register Setup Time before Clock 30 GLB Register Hold Time after Clock 31 GLB Register Clock to Output Delay 32 GLB Register Reset to Output Delay 33 GLB Product Term Reset to Register Delay 34 GLB Product Term Output Enable to I/O Cell Delay 35 GLB Product Term Clock Delay 36 ORP Delay 37 ORP Bypass Delay 38 Output Buffer Delay 39 Output Slew Limited Delay Adder 40 I/O Cell OE to Output Enabled 41 I/O Cell OE to Output Disabled 42 Global Output Enable 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 45 Global Reset to GLB
torp torpbp
Outputs
tob tsl toen todis tgoe
Clocks
tgy0 tgy1/2
Global Reset
tgr
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros.
Table 2-0036A/2032VE
7
Specifications ispLSI 2032VE
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER Inputs #2 DESCRIPTION -135 -110 UNITS
MIN. MAX. MIN. MAX. - - - - - - - - - 1.1 2.9 - - - - 1.7 - - - - - - - 1.7 1.9 - 0.8 1.7 0.9 3.9 2.9 4.4 4.4 4.4 1.0 - - 0.9 1.8 6.1 6.9 4.1 1.5 0.5 1.4 2.0 3.4 3.4 2.6 1.7 1.9 5.3 - - - - - - - - - 1.4 4.1 - - - - 2.5 - - - - - - - 1.8 2.0 - 1.3 2.5 1.2 4.8 3.4 5.4 5.4 5.4 1.4 - - 1.0 2.7 7.1 8.6 4.4 1.9 0.9 1.8 2.0 3.4 3.4 3.6 1.8 2.0 7.1
tio tdin
GRP
20 Input Buffer Delay 21 Dedicated Input Delay 22 GRP Delay 23 4 Product Term Bypass Path Delay (Combinatorial) 24 4 Product Term Bypass Path Delay (Registered) 25 1 Product Term/XOR Path Delay 26 20 Product Term/XOR Path Delay 27 XOR Adjacent Path Delay
3
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tgrp
GLB
t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck
ORP
28 GLB Register Bypass Delay 29 GLB Register Setup Time before Clock 30 GLB Register Hold Time after Clock 31 GLB Register Clock to Output Delay 32 GLB Register Reset to Output Delay 33 GLB Product Term Reset to Register Delay 34 GLB Product Term Output Enable to I/O Cell Delay 35 GLB Product Term Clock Delay 36 ORP Delay 37 ORP Bypass Delay 38 Output Buffer Delay 39 Output Slew Limited Delay Adder 40 I/O Cell OE to Output Enabled 41 I/O Cell OE to Output Disabled 42 Global Output Enable 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 45 Global Reset to GLB
torp torpbp
Outputs
tob tsl toen todis tgoe
Clocks
tgy0 tgy1/2
Global Reset
tgr
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros.
Table 2-0036A/2032VE
8
Specifications ispLSI 2032VE
ispLSI 2032VE Timing Model
I/O Cell
GRP Feedback
GLB
ORP
I/O Cell
Ded. In
#21 I/O Delay #20 GRP #22
Comb 4 PT Bypass #23 Reg 4 PT Bypass #24 20 PT XOR Delays #25, 26, 27 D RST GLB Reg Bypass #28 GLB Reg Delay Q #29, 30, 31, 32 ORP Bypass #37 ORP Delay #36 #38, 39 I/O Pin (Output)
I/O Pin (Input)
Reset
#45
Control RE PTs OE #33, 34, CK 35 Y0,1,2 GOE 0 #43, 44 #42
#40, 41
0491/2032VE
Derivations of tsu, th and tco from the Product Term Clock tsu
= = = 2.5ns = = = = 2.3ns = = = = 7.3ns = Logic + Reg su - Clock (min) (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min)) (#20 + #22 + #26) + (#29) - (#20 + #22 + #35) (0.6 + 0.7 + 2.2) + (6.8) - (0.6 + 0.7 + 0.5) Clock (max) + Reg h - Logic (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor) (#20 + #22 + #35) + (#30) - (#20 + #22 + #26) (0.6 + 0.7 + 2.8) + (1.7) - (0.6 + 0.7 + 2.2) Clock (max) + Reg co + Output (tio + tgrp + tptck(max)) + (tgco) + (torp + tob) (#20 + #22 + #35) + (#31) + (#36 + #38) (0.6 + 0.7 + 2.8) + (0.7) + (1.3 + 1.2)
th
tco
Note: Calculations are based on timing specifications for the ispLSI 2032VE-225L.
Table 2-0042/2032VE
9
Specifications ispLSI 2032VE
Power Consumption
Power consumption in the ispLSI 2032VE device depends on two primary factors: the speed at which the device is operating and the number of product terms Figure 3. Typical Device Power Consumption vs fmax
150
used. Figure 3 shows the relationship between power and operating speed.
125 ispLSI 2032VE-225
100
ICC (mA)
75
ispLSI 2032VE-180 and slower
50
25
0
25
50
75
100
125
150
175
200
225
fmax (MHz)
Notes: Configuration of two 16-bit counters Typical current at 3.3V, 25 C
ICC can be estimated for the ispLSI 2032VE using the following equation: For ispLSI 2032VE-225: ICC(mA) = 4.5 + (# of PTs * 1.29) + (# of nets * Max freq * 0.0068) For ispLSI 2032VE-180 and slower: ICC(mA) = 4.5 + (# of PTs * 1.05) + (# of nets * Max freq * 0.0068) Where: # of PTs = Number of product terms used in design # of nets = Number of signals used in device Max freq = Highest clock frequency to the device (in MHz) The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified.
0127A/2032VE
10
Specifications ispLSI 2032VE
Signal Descriptions
Signal Name GOE 0 Y0 RESET/Y1 Global Output Enable Pin Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs on the device. This pin performs two functions: (1) Dedicated clock input. This clock input is brought into the Clock Deistribution Network and can optionally be routed to any GLB and/or I/O cell on the device. (2) Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Input - Dedicated in-system programming Boundary Scan Enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK controls become active. Input - This pin performs two functions. When BSCAN is logic low, it functions as an input pin to load programming data into the device. TDI/IN0 is also used as one of the two control pins for the ISP State Machine. When BSCAN is high, it functions as a dedicated input pin. Input - When in ISP Mode, controls operation of the ISP State Machine. Output/Input - This pin performs two functions. When BSCAN is logic low, it functions as an output pin pin to read serial shift register data. When BSCAN is high, it functions as a dedicated input pin. Input - This pin performs two functions. When BSCAN is logic low, it functions as a clock pin for the Serial Shift Register. When BSCAN is high, it functions as a dedicated clock input. This clock input is brought into the Clock Distribution Network and can optionally be routed to any GLB and/or I/O cell on the device. Ground (GND) Vcc No Connect Input/Output pins - These are the general purpose I/O pins used by the logic array. Description
BSCAN TDI/IN 0
TMS/NC1 TDO/IN 1 TCK/Y2
GND VCC NC1 I/O
Signal Locations
Signal GOE 0 Y0 RESET/Y1 BSCAN TDI/IN 0 TMS/NC1 TDO/IN 1 TCK/Y2 GND VCC NC1 40 5 29 7 8 30 18 27 17, 39 6, 28 -- 44-Pin TQFP 2 11 35 13 14 36 24 33 1, 23 12, 34 -- 44-Pin PLCC 43 5 31 7 8 32 19 29 18, 42 6, 30 12, 24, 36, 48 48-Pin TQFP A4 C1 D7 D1 E2 C6 G4 E7 C4, E4 D3, D5 A1, A7, D4, G1, G7 49-Ball caBGA
I/O Locations
Signal I/O 0 - I/O 6 I/O 7 - I/O 13 I/O 14 - I/O 20 I/O 21 - I/O 27 I/O 28 - I/O 31 44-Pin TQFP 9, 10, 11, 12, 13, 14, 15 44-Pin PLCC 15, 16, 17, 18, 19, 20, 21 48-Pin TQFP 9, 10, 11, 13, 14, 15, 16 17, 20, 21, 22, 23, 25, 26 27, 28, 33, 34, 35, 37, 38 39, 40, 41, 44, 45, 46, 47 1, 2, 3, 4 49-Ball caBGA E1, F2, F1, E3, F3, G2, F4 G3, F5, G5, F6, G6, E5, E6 F7, D6, C7, B6, B7, C5, B5 A6, B4, A5, B3, A3, B2, A2 C3, C2, B1, D2
16, 19, 20, 21, 22, 23, 24 22, 25, 26, 27, 28, 29, 30 25, 26, 31, 32, 33, 34, 35 31, 32, 37, 38, 39, 40, 41 36, 37, 38, 41, 42, 43, 44 42, 43, 44, 3, 4, 5, 6 1, 2, 3, 4 7, 8, 9, 10
1. NC pins are not to be connected to any active signals, VCC or GND.
11
Specifications ispLSI 2032VE
Pin Configuration
ispLSI 2032VE 44-Pin TQFP Pinout Diagram
GOE 0 I/O 27 I/O 26 I/O 25 I/O 24 GND I/O 23 I/O 22 I/O 21 I/O 20 I/O 19
33 32 31 30
44 43 42 41 40 39 38 37 36 35 34 I/O 28 I/O 29 I/O 30 I/O 31 Y0 VCC BSCAN TDI/IN 0 I/O 0 I/O 1 I/O 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 I/O 18 I/O 17 I/O 16 TMS/NC1 RESET/Y1 VCC TCK/Y2 I/O 15 I/O 14 I/O 13 I/O 12
ispLSI 2032VE
Top View
29 28 27 26 25 24 23
GND TDO/IN 1
I/O 9 I/O 10 I/O 11
I/O 3
I/O 4 I/O 5
I/O 6
I/O 7
I/O 8
0851/2032VE
1. NC pins are not to be connected to any active signals, VCC or GND.
Pin Configuration
ispLSI 2032VE 44-Pin PLCC Pinout Diagram
GOE 0 I/O 27 I/O 26 I/O 25 I/O 24 GND I/O 23 I/O 22 I/O 21 I/O 20 I/O 19
39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28
6 5 4 3 2 1 44 43 42 41 40 I/O 28 I/O 29 I/O 30 I/O 31 Y0 VCC BSCAN TDI/IN 0 I/O 0 I/O 1 I/O 2 7 8 9 10 11 12 13 14 15 16 17 I/O 18 I/O 17 I/O 16 TMS/NC1 RESET/Y1 VCC TCK/Y2 I/O 15 I/O 14 I/O 13 I/O 12
ispLSI 2032VE
Top View
TDO/IN 1
I/O 9 I/O 10 I/O 11
I/O 3
I/O 4 I/O 5
I/O 6
I/O 7
GND
I/O 8
0123/2032VE
1. NC pins are not to be connected to any active signals, VCC or GND.
12
Specifications ispLSI 2032VE
Pin Configuration
ispLSI 2032VE 48-Pin TQFP Pinout Diagram
GOE 0 I/O 27 I/O 26 I/O 25 I/O 24 GND I/O 23 I/O 22 NC2 I/O 21 I/O 20 I/O 19
48 47 46 45 44 43 42 41 40 39 38 37 I/O 28 I/O 29 I/O 30 I/O 31 Y0 VCC BSCAN
1TDI/IN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
1TDO/IN
36 35 34 33
NC2 I/O 18 I/O 17 I/O 16 TMS/NC2 RESET/Y11 VCC TCK/Y21 I/O 15 I/O 14 I/O 13 I/O 12
ispLSI 2032VE
Top View
32 31 30 29 28 27 26 25
0
I/O 0 I/O 1 I/O 2 2NC
I/O 9 I/O 10 I/O 11 2NC
GND
1
I/O 3
I/O 4 I/O 5
I/O 6
I/O 7
I/O 8
48TQFP/2032VE
1. Pins have dual function capability. 2. NC pins are not to be connected to any active signals, VCC or GND.
Signal Configuration
ispLSI 2032VE 49-Ball caBGA Signal Diagram
7 6 5 4 3 2 1
A B C D E F G
NC1 I/O 18 I/O 16
RESET/ Y1
I/O 21 I/O 17 TMS/ NC1 I/O 15 I/O 13 I/O 10 I/O 11
I/O 23 I/O 20 I/O 19 VCC I/O 12 I/O 8 I/O 9
GOE 0 I/O 22 GND
I/O 25 I/O 24 I/O 28 VCC I/O 3 I/O 4 I/O 7
I/O 27 I/O 26 I/O 29 I/O 31 TDI/ IN0 I/O 1 I/O 5
NC1
A B C D E F G
I/O 30 Y0
NC1
BSCAN
TCK/ Y2 I/O 14 NC1
GND I/O 6 TDO/ IN1
I/O 0 I/O 2 NC1
ispLSI 2032VE Bottom View
7
6
5
4
3
2
1
49-BGA/2032VE
1. NCs are not to be connected to any active signals, VCC or GND. Note: Ball A1 indicator dot on top side of package.
13
Specifications ispLSI 2032VE
Part Number Description
ispLSI 2032VE - XXX
Device Family Device Number 2032VE Speed 225 = 225 MHz fmax 180 = 180 MHz fmax 135 = 135 MHz fmax 110 = 110 MHz fmax
X XXX X
Grade Blank = Commercial I = Industrial Package T44 = 44-Pin TQFP T48 = 48-Pin TQFP J44 = 44-Pin PLCC B49 = 49-Ball caBGA Power L = Low
0212A/2032VE
ispLSI 2032VE Ordering Information
COMMERCIAL
FAMILY fmax (MHz) 225 225 225 225 180 180 180 180 135 135 135 135 110 110 110 110 tpd (ns) 4.0 4.0 4.0 4.0 5.0 5.0 5.0 5.0 7.5 7.5 7.5 7.5 10 10 10 10 ORDERING NUMBER ispLSI 2032VE-225LT44 ispLSI 2032VE-225LT48 ispLSI 2032VE-225LJ44 ispLSI 2032VE-225LB49 ispLSI 2032VE-180LT44 ispLSI 2032VE-180LT48 ispLSI 2032VE-180LJ44 ispLSI 2032VE-180LB49 ispLSI 2032VE-135LT44 ispLSI 2032VE-135LT48 ispLSI 2032VE-135LJ44 ispLSI 2032VE-135LB49 ispLSI 2032VE-110LT44 ispLSI 2032VE-110LT48 ispLSI 2032VE-110LJ44 ispLSI 2032VE-110LB49 PACKAGE 44-Pin TQFP 48-Pin TQFP 44-Pin PLCC 49-Ball caBGA 44-Pin TQFP 48-Pin TQFP 44-Pin PLCC 49-Ball caBGA 44-Pin TQFP 48-Pin TQFP 44-Pin PLCC 49-Ball caBGA 44-Pin TQFP 48-Pin TQFP 44-Pin PLCC 49-Ball caBGA
Table 2-0041A/2032VE
ispLSI
INDUSTRIAL
FAMILY ispLSI fmax (MHz) 180 tpd (ns) 5.0 ORDERING NUMBER ispLSI 2032VE-180LT44I PACKAGE 44-Pin TQFP
Table 2-0041B/2032VE
14

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